NOR type flash memories are typically used to store programs or codes for cellular phones. NOR type flash memory has a structure with a single memory cell connected between a bit line and a ground line. NOR type flash memories are of lower density compared with NAND type flash memories, and need further to be miniaturized in order to increase memory capacity. Recently, in response to demands for cost reduction and increasing memory capacity, still further miniaturization has been proceeded for NOR type flash memories.
NOR type flash memories adopt a method for injecting electrons into a floating gate by Channel-Hot-electrons during programming operation. In this programming method, by flowing a large current of several micro-amperes through a channel, large amounts of electrons flow from a source to a drain. The large amount of electrons flowing into the drain from the source generate electron hole pairs in the drain side depletion layer. By applying a high voltage to a control gate, a portion of the electron hole pairs obtains acceleration energy by the electrical voltage across the horizontal direction, holes move toward the substrate and a portion of the electrons obtain enough energy to become Hot-electrons to overcome an energy barrier of the gate oxide film and is injected into the floating gate. Therefore, it is necessary to apply high voltages across the source and the drain and to the control gate at the same time. In other words, Hot-electron injection will not happen if only one of either the source and the drain or the control gate is applied with a high voltage.
It turns out that a large drain current is needed for programming a cell by the Channel-Hot-electron programming operation using this physical principal. An energy greater than the energy barrier of a silicon dioxide film which is in between the floating gate and the channel should be around −4 eV in order to render Hot-electrons to be injected into the floating gate. Moreover, the potential difference between the drain and the source is typically around 5V.
At the same time, as mentioned, it is difficult to make the potential difference between the drain and the source small despite the advances in memory cell miniaturization. When the miniaturization of memory cells is advanced and the channel length is reduced, a punch-through voltage will be lowered and a leakage current will flow through unselected memory cells which are connected to a common programming bit line. As a result, it might bring fatal error operations such as it can not operate correctly.
Therefore, a method is suggested whereby a negative voltage is applied to the memory cell substrate during programming operation of a NOR type flash memory, and to reduce a voltage across drain and source to around 3V (J. D. Bude, et al., “Secondary Electron Flash—a High Performance, Low Power Flash Technology for 0.35 um and Below”, IEDM, hereinafter called “Document 1”).
The outline configuration of the NOR type flash memory 100 implementing the programming method described in the Document 1 is shown in FIG. 6. The NOR type flash memory 100 has a memory cell array 101. For conveniences of explanation, only 3×3 memory cells and corresponding bit lines B0-B2 and word lines W0-W2 are shown in FIG. 6. 102 is a Column Decoder, 103 is a Row Decoder, 104 is a Drain Charge Pump (DCP), 105 is a Sense Amplifier (S/A), 106 is a Negative Charge Pump (NCP) and 107 is a Source Line Decoder.
According to the programming operation of the NOR type flash memory 100 shown in FIG. 6, a larger electrical field is applied to the depletion layer of the drain side, hole-electron pairs are generated by electrons running toward the drain, and the holes are flown into the substrate by a horizontal electrical field. At the same time, electrons from the electron hole pairs flow into the drain in a vertical direction. The electrons flowing in the vertical direction obtain an energy greater than the energy barrier of a silicon oxide film and are injected into the floating gate (Masataka Kato, et al., “A Shallow-Trench-Isolation Flash Memory Technology with a Source-Bias Programming Method”, IEDM' 96, hereinafter called “Document 2”) This phenomenon is called secondary electron collision principle and is considered to be promising and draw s attention as a method to enable shrinking of channel length L of a memory cell.
Here, assuming the drain electron current flowing between the source and the drain of the NOR type flash memory 100 of FIG. 6 is Iprg,e (Electron Current), the current flowing from the drain charge pump 104 is Idcp, the current flowing from the channel into the substrate (substrate hole current) is Iprg,h (Hole Current), and the current flowing into the negative charge pump 106 is Incp, the following relationships are met:Idcp>Iprg,e   (1)Incp>Iprg,h   (2)Iprg,e≈Iprg,h   (3)
However, the typical programming operation described in Document 1 has the following problem. In the programming operation method of the NOR type flash memory 100, the substrate hole currents Iprg,h which is almost equal to the drain electron currents Iprg,e flows as shown in the relationship (3) When designing a NOR type flash memory, a negative voltage needed for programming is generated from an external negative voltage supply and is provided by the negative charge pump (NCP) 106. Moreover, a drain voltage needed for programming is also generated from the external positive voltage source and provided by the drain charge pump (DCP) 104. In order to maintain stable programming operations, it is necessary to keep the currents and voltages that the memory cell requires to be constant, therefore, the negative charge pump (NCP) 106 and the drain charge pump (DCP) 104 are required to have power to supply enough voltage and current. Therefore, it is necessary to make the circuit area (Dimension) of each of the pumps larger. However, making the circuit area (Dimension) larger renders making the circuit area of the entire peripheral circuit, including the pumps, larger, thereby increasing production costs.